ceClub

Secure Logical Isolation for Multi-tenancy in Cloud Storage

Dr. Hillel Kolodner

Systems Technologies department, IBM Haifa Research Lab.

Storage cloud systems achieve economies of scale by serving multiple tenants from a shared pool of servers and disks. This leads to the commingling of data from different tenants on the same devices. Typically, a request is processed by an application running with sufficient privileges to access any tenant's data; this application authenticates the user and authorizes the request prior to carrying it out. Since the only protection is at the application level, a single vulnerability threatens the data of all tenants, and could lead to cross-tenant data leakage, making the cloud much less secure than dedicated physical resources.

To provide security close to physical isolation while allowing complete resource pooling, we propose Secure Logical Isolation for Multi-tenancy (SLIM). SLIM incorporates the first complete security model and set of principles for the safe logical isolation between tenant resources in a cloud storage system, as well as a set of mechanisms for implementing the model. These principles lead to the potentially costly conclusion that each request should be handled by a new process. We present a detailed design, implementation and performance analysis of a process factory to greatly reduce the cost while still preserving secure isolation. Finally, we show how to implement SLIM for OpenStack Swift and present performance results, showing SLIM with our optimizations provides an order of magnitude improvement over a naive implementation of process isolation.

Authors: Michael Factor, David Hadas, Aner Hamama, Nadav Har'el, Hillel Kolodner, Anil Kurmus, Eran Rom, Alexandra Shulman-Peleg and Alessandro Sorniotti.

Bio: Hillel Kolodner is a Senior Technical Staff Member in the Systems Technologies department at the IBM Haifa Research Lab. In the past he has worked on the implementation of Java for multiprocessor servers, especially on automatic memory management (garbage collection). Recently, he has worked on virtualization and management technologies for cloud computing. Currently, he is working on cloud object stores and is the PI for VISION Cloud , an European Commission FP7 Integrated Project developing storage cloud technologies. Hillel holds a Ph.D. and M.S. in Computer Science from the Massachusetts Institute of Technology, and a B.A. in Mathematics and a B.S.E. in Computer Science from the University of Pennsylvania.

Spinal Codes

Jonathan Perry

MIT, Computer Science and Artificial Intelligence Lab.

Handling noise and interference in wireless networks requires adaptive, high-performance error correction. Spinal codes are a new rateless error correcting code that iteratively applies a hash function to message bits, ensuring that two input messages that differ in even one bit produce very different coded sequences after the point at which they differ. Spinal codes offer a flexible tradeoff between computational cost and performance. Because spinal codes are rateless, they automatically adapt to changing channel conditions.

The resulting system achieves better throughput than LDPC and Raptor codes, and despite the large state space induced by the hash output, the message can be recovered efficiently; a preliminary hardware prototype decodes at 10Mbps.

No prior knowledge of coding theory is required.

More information at http://nms.csail.mit.edu/spinal/

Bio: Jonathan Perry received a B.Sc in CS from Tel-Aviv University in 2003. Jonathan worked in high performance computing and in distributed systems until 2010, when he joined MIT's Ph.D. program. Co-advised by Hari Balakrishnan and Devavrat Shah, Jonathan is currently working on error correcting codes and efficient network transport.

Multi-core, Mega-nonsense

Prof. Yale Patt (Henry Taub Distinguished Visitor)

University of Texas at Austin

Multicore has been around for several years now, and we hear it touted as the panacea of everything. ...until recently, that is. As expected, the hype has generated a lot of nonsense. We are told that multicore came about as a solution to a performance problem, that multicore allows you to run your problems at half the frequency and save power, that ILP is dead, that Moore's Law means we can put thousands (perhaps millions?) of cores on a single silicon die, that hardware works sequentially, and that abstraction is a pure good. Most recently, the term dark silicon has been coined as one of the bad consequences of the continual viability of Moore's Law. In this talk, I propose to examine some of the nonsense, and in particular, see if some of these "bugs" can be turned into "features."

Bio: Yale Patt is a teacher at the local public university in Austin, Texas. He has enjoyed almost 50 years (so far) in computing: teaching, doing research, and consulting. Some of his research (e.g., HPS, branch prediction) have found their way into successful microprocessors. His unconventional but CORRECT approach to introducing serious students to computing has found its way into the curriculum of more than 100 universities worldwide and a breakaway textbook,"Intro to Computing, from bits and gates to C and beyond." He earned the obligatory degrees from reputable universities and has received more than enough awards for his research and teaching. More detail can be found on his web site: www.ece.utexas.edu/~patt.